The present invention relates to a semiconductor memory component.
Although the problem area on which the invention is based is described below with reference to a random access memory, it is not restricted thereto, but rather relates quite generally to semiconductor memory components.
Such a random access memory is for example a DRAM (dynamic random access memory) having a multiplicity of memory cells. Each of the individual memory cells comprises a transistor and a capacitor. Information is stored in the form of a quantity of charge in the capacitor, and it can be accessed by means of the transistor.
For reliable operation of the DRAM, the capacitor must have a minimum capacitance. The capacitance of the capacitor is crucially determined by the area of the electrodes. Therefore, a minimum area of the electrodes is required.
Leakage currents of the transistor discharge the capacitor. This discharge may be compensated for on the one hand by more generous dimensioning of the capacitor. On the other hand, it is also possible to use transistors having a good blocking behavior.
In endeavoring to integrate a larger number of memory cells on an acceptable area, the lateral dimensions of the capacitors and transistors can be reduced. In order that the area of the electrodes does not fall below the minimum area of said electrodes despite the reduced lateral dimensions of said electrodes, vertical electrodes are produced in the case of which the electrodes is placed increasingly into the depth of the semiconductor body. However, the outlay for producing these vertical electrodes increases as the lateral dimensioning decreases.
Another approach for producing memory cells provides for injecting charge carriers into a body region, the drain zone, the source zone and the gate electrode being arranged in said body region or on the body region. The charges in the body region shift the threshold voltage of the transistor typically by several hundred millivolts. Consequently, a body region with injected charges and without injected charges can be distinguished on the basis of the switching behavior of the transistor. Therefore, S. Okhonin et al. in IEEE Electron Device Letters, Vol. 23, No. 2, page 85, February 2002, proposed producing memory cells based on this principle. It is disadvantageous, however, that the storage durations of the charges in the body region are only in the range of a few milliseconds instead of corresponding to the required specification of a storage duration of approximately 250 ms for a memory cell.